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? semiconductor components industries, llc, 2009 september, 2009 ? rev. 5 1 publication order number: amis ? 30624/d amis-30624, ncv70624 i 2 c micro-stepping motor driver introduction the amis ? 30624/ncv70624 is a single ? chip micro ? stepping motor driver with a position controller and control/diagnostic interface. it is ready to build intelligent peripheral systems where up to 32 drivers can be connected to one i 2 c master. this significantly reduces system complexity. the chip receives positioning instructions through the bus and subsequently drives the stator coils so the two ? phase stepper motor moves to the desired position. the on ? chip position controller is configurable (otp or ram) for different motor types, positioning ranges and parameters for speed, acceleration and deceleration. micro ? stepping allows silent motor operation and increased positioning resolution. the advanced motion qualification mode enables verification of the complete mechanical system in function of the selected motion parameters. the amis ? 30624/ncv70624 can easily be connected to an i 2 c bus where the i 2 c master can fetch specific status information like actual position, error flags, etc. from each individual slave node. an integrated sensorless step ? loss detection prevents the positioner from loosing steps and stops the motor when running into stall. this enables silent, yet accurate position calibrations during a referencing run and allows semi ? closed loop operation when approaching the mechanical end ? stops. the chip is implemented in i2t100 technology, enabling both high voltage analog circuitry and digital functionality on the same chip. the ncv70624 is fully compatible with the automotive voltage requirements. product features motor driver ? micro ? stepping t echnology ? sensorless step ? loss detection ? peak current up to 800 ma ? fixed frequency pwm current ? control ? selectable pwm frequency ? automatic selection of fast and slow decay mode ? no external fly ? back diodes required ? 14 v/24 v compliant ? motion qualification mode (note 1) controller with ram and otp memory ? position controller ? configurable speeds and acceleration ? input to connect optional motion switch i 2 c interface ? bi ? directional 2 ? wire bus for inter ic control ? field programmable node addresses ? full diagnostics and status information protection ? overcurrent protection ? undervoltage management ? open ? circuit detection ? high temperature warning and management ? low temperature flag emi compatibility ? high voltage outputs with slope control patents ? us 7,271,993 ? us 7,288,956 ? this is a pb ? free device ? ncv prefix for automotive and other applications requiring site and control changes 1. not applicable for ?product versions ncv70624dw010g, NCV70624DW010R2G? http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information soic ? 20 4 or dw010 suffix case 751aq nqfp ? 32 5 suffix case 560aa
amis ? 30624, ncv70624 http://onsemi.com 2 applications the amis ? 30624/ncv70624 is ideally suited for small positioning applications. target markets include: automotive (headlamp alignment, hvac, idle control, cruise control), industrial equipment (lighting, fluid control, labeling, process control, xyz tables, robots) and building automation (hvac, surveillance, satellite dish, renewable energy systems). suitable applications typically have multiple axes or require mechatronic solutions with the driver chip mounted directly on the motor. table 1. ordering information part no. peak current end market/version package* shipping ? amis30624c6244g 800 ma industrial high voltage version soic ? 20 (pb ? free) tube/tray amis30624c6244rg 800 ma soic ? 20 (pb ? free) tape & reel amis30624c6245g 800 ma nqfp ? 32 (7 x 7 mm) (pb ? free) tube/tray amis30624c6245rg 800 ma nqfp ? 32 (7 x 7 mm) (pb ? free) tape & reel ncv70624dw010g 800 ma automotive high temperature version soic ? 20 (pb ? free) tube/tray NCV70624DW010R2G 800 ma soic ? 20 (pb ? free) tape & reel *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. quick reference data table 2. absolute maximum ratings parameter min max unit v bb , v hw , v swi supply voltage, hardwired address and swi pins ? 0.3 +40 (note 2) v t j junction temperature range (note 3) ? 50 +175 ? c t st storage temperature ? 55 +160 ? c v esd (note 4) human body model (hbm) electrostatic discharge voltage on pins ? 2 +2 kv machine model (mm) electrostatic discharge voltage on pins ? 200 +200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 2. for limited time: v bb < 0.5 s, swi and hw pins <1.0 s. 3. the circuit functionality is not guaranteed. 4. hbm according to aec ? q100: eia ? jesd22 ? a114 ? b (100 pf via 1.5 k ) and mm according to aec ? q100: eia ? jesd22 ? a115 ? a. table 3. operating ranges parameter min max unit v bb supply voltage +6.5 +29 v t j operating temperature range ? 40 +165 ? c
amis ? 30624, ncv70624 http://onsemi.com 3 table of contents general description 1 ............................ product features 1 .............................. applications 2 .................................. ordering information 2 ........................... quick reference data 2 .......................... maximum ratings 2 ............................. block diagram 3 ................................ pin description 4 ............................... package thermal resistance 5 ..................... dc parameters 6 ................................ ac parameters 8 ................................ typical application 10 ........................... positioning parameters 11 ......................... structural description 14 ......................... functions description 15 ......................... position controller 15 ............................ main control and register 22 ...................... autarkic functionality in undervoltage condition 24 ... otp register 25 ................................ priority encoder 30 .............................. motordriver 32 ................................. i 2 c bus description 37 ........................... i 2 c application commands 42 ..................... package outlines 50 ............................. figure 1. block diagram i 2 c ? bus interface oscillator vref temp sense voltage regulator tst2 vbb vdd gnd motxp motxn main control registers otp ? rom 4mhz charge pump cpn cpp vcp stall detection position controller controller tst1 motyp motyn pwm regulator y pwm regulator x i ? sense decoder sinewave table dac?s amis ? 30624, ncv70624 hw swi sda sck i ? sense
amis ? 30624, ncv70624 http://onsemi.com 4 1 2 3 5 4 6 7 8 24 23 22 20 21 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 xp vbb swi nc sda xp vbb vbb cpn cpp vcp yn vbb yn vbb vbb yp xn gnd gnd xn yp gnd gnd sck vdd gnd tst1 tst2 hw gnd nc amis ? 30624 17 18 19 20 1 2 3 4 sda gnd swi gnd sck motxp vbb vdd 16 15 14 13 12 11 5 6 7 8 9 10 gnd gnd motxn motyp motyn tst1 tst2 hw cpn cpp vbb vcp soic ? 20 figure 2. soic ? 20 and nqfp ? 32 pin ? out amis ? 30624 (top view) ncv70624 ncv70624 table 4. pin description pin name pin description soic ? 20 nqfp ? 32 sda i 2 c serial data line 1 8 sck i 2 c serial clock line 2 9 v dd internal supply (needs external decoupling capacitor) 3 10 gnd ground, heat sink 4, 7, 14, 17 11, 14, 25, 26, 31, 32 tst1 test pin (to be tied to ground in normal operation) 5 12 tst2 test pin (to be left open in normal operation: internally pulled up) 6 13 hw hard wired address bit 8 15 cpn negative connection of pump ? capacitor (charge pump) 9 17 cpp positive connection of pump ? capacitor (charge pump) 10 18 vcp charge ? pump filter ? capacitor 11 19 v bb battery voltage supply 12, 19 3, 4, 5, 20, 21, 22 motyn negative end of phase y coil 13 23, 24 motyp positive end of phase y coil 15 27, 28 motxn negative end of phase x coil 16 29, 30 motxp positive end of phase x coil 18 1, 2 swi switch input 20 6 nc not connected (to be tied to ground) 7, 16
amis ? 30624, ncv70624 http://onsemi.com 5 package thermal resistance the amis ? 30624/ncv70624 is available in soic ? 20 or optimized nqfp ? 32 packages. for cooling optimizations, the nqfp has an exposed thermal pad which has to be soldered to the pcb ground plane. the ground plane needs thermal vias to conduct the head to the bottom layer. figures 3 and 4 give examples for good power distribution solutions. for precise thermal cooling calculations the major thermal resistances of the devices are given. the thermal media to which the power of the devices has to be given are: ? static environmental air (via the case) ? pcb board copper area (via the device pins and exposed pad) the thermal resistances are presented in table 5: dc parameters. the major thermal resistances of the device are the rth from the junction to the ambient (rthja) and the overall rth from the junction to the leads (rthjp). the nqfp device is designed to provide superior thermal performance. using an exposed die pad on the bottom surface of the package is mainly contributing to this performance. in order to take full advantage of the exposed pad, it is most important that the pcb has features to conduct heat away from the package. a thermal grounded pad with thermal vias can achieve this. in the table below, one can find the values for the rthja and rthjp, simulated according to the jesd ? 51 norm: package rth junction ? to ? leads and exposed pad ? rthjp rth junction ? to ? leads rthjp rth junction ? to ? ambient rthja (1s0p) rth junction ? to ? ambient rthja (2s2p) soic ? 20 19 62 39 nqfp ? 32 0,95 60 30 the rthja for 2s2p is simulated conform to jesd ? 51 as follows: ? a 4 ? layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used ? board thickness is 1.46 mm (fr4 pcb material) ? the 2 signal layers: 70 m thick copper with an area of 5500 mm 2 copper and 20% conductivity ? the 2 power internal planes: 36 m thick copper with an area of 5500 mm 2 copper and 90% conductivity the rthja for 1s0p is simulated conform to jesd ? 51 as follows: ? a 1 ? layer printed circuit board with only 1 layer ? board thickness is 1.46 mm (fr4 pcb material) ? the layer has a thickness of 70 m copper with an area of 5500 mm 2 copper and 20% conductivity ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ????????????? ?? ?? ?? ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? ???????????? figure 3. example of soic ? 20 pcb ground plane layout (preferred layout at top and bottom) figure 4. example of nqfp ? 32 pcb ground plane layout (preferred layout at top and bottom) nqfp ? 32 soic ? 20
amis ? 30624, ncv70624 http://onsemi.com 6 dc parameters the dc parameters are guaranteed overtemperature and v bb in the operating range, unless otherwise specified. convention: currents flowing into the circuit are defined as positive. table 5. dc parameters symbol pin(s) parameter test conditions min typ max unit motordriver i msmax,peak motxp motxn motyp motyn max current through motor coil in normal operation v bb = 14 v 800 ma i msmax,rms max rms current through coil in normal operation v bb = 14 v 570 ma i msabs absolute error on coil current (note 5) v bb = 14 v ? 10 10 % i msrel matching of x & y coil currents v bb = 14 v ? 7 0 7 % r ds(on) on resistance for each motor pin at i msmax (note 6) v bb = 12 v, t j = 50 ? c 0.50 1 v bb = 8 v, t j = 50 ? c 0.55 1 v bb = 12 v, t j = 150 ? c 0.70 1 v bb = 8 v, t j = 150 ? c 0.85 1 i msl pulldown current hiz mode, v bb = 7.8 v 2 ma i 2 c serial interface v il sda sck input level low (note 11) ? 0.5 0.3 * v dd v v ih input level high (note 12) 0.7 * v dd v dd + 0.5 v v nl noise margin at the low level for each connected device (including hysteresis) 0.1 * v dd v v nh noise margin at the high level for each connected device (including hysteresis) 0.2 * v dd thermal warning & shutdown t tw thermal warning (notes 7 and 8) 138 145 152 ? c t tsd thermal shutdown (note 9) t tw + 10 ? c t low low temperature warning (note 9) t tw ? 155 ? c supply and voltage regulator v bbotp v bb supply voltage for otp zapping (note 10) 9.0 10.0 v uv 1 stop voltage high threshold 7.8 8.4 8.9 v uv 2 stop voltage low threshold 7.1 7.5 8.0 v i bat total current consumption unloaded outputs v bb = 29 v 3.50 10.0 ma 5. tested in production for 800 ma, 400 ma, 200 ma and 100 ma current settings for both x and y coil. 6. not measured in production. guaranteed by design. 7. parameter guaranteed by trimming relevant otp?s in production test at 143 ? c ( ? 5 ? c) and v bb = 14 v. 8. no more than 100 cumulated hours in life time above tw. 9. thermal shutdown and low temperature warning are derived from thermal warning. guaranteed by design. 10. a buffer capacitor of minimum 100 f is needed between v bb and gnd. short connections to the power supply are recommended. 11. if input voltages < ? 0.3 v, than a resistor between 22 to 100 needs to be put in series. 12. if the i 2 c ? bus is operated in fast mode v ihmin = 0.7 * v dd .
amis ? 30624, ncv70624 http://onsemi.com 7 table 5. dc parameters symbol pin(s) parameter test conditions min typ max unit supply and voltage regulator v dd v dd regulated internal supply (note 13) 8 v < v bb < 29 v 4.75 5 5.50 v v ddreset digital supply reset level @ power down (note 14) 4.5 v i ddlim current limitation pin shorted to ground v bb = 14 v 45 ma switch input and hardwire address input rt_ off swi hw switch open resistance (note 15) 10 k rt_ on switch on resistance (note 15) switch to gnd or v bb 2 k v bb_sw v bb range for guaranteed operation of swi and hw 6 29 v i lim_sw current limitation short to gnd or v bat v bb = 29 v 20 30 45 ma test pin v ihigh tst input level high v bb = 14 v 0.7 * v dd v v ilow input level low v bb = 14 v 0.3 * v dd v hw hyst hysteresis v bb = 14 v 0.075 * v dd v charge pump v cp vcp output voltage 6 v ? v bb ? 14 v 2 * v bb ? 2.5 v 14 v ? v bb ? 30 v v bb + 10 v bb + 15 v c buffer external buffer capacitor 220 470 nf c pump cpp cpn external pump capacitor 220 470 nf motion qualification mode output (note 16) v out swi output voltage swing testbemf i 2 c command 0 ? 4,85 v r out output impedance service mode i 2 c command 2 k av gain = v swi / v bemf service mode i 2 c command 0.50 package thermal resistance values rth ja so thermal resistance junction to ambient (2s2p) simulated conform jedec jesd51 39 k/w rth jp so thermal resistance junction to leads 19 k/w rth ja nq thermal resistance junction to ambient (2s2p) 30 k/w rth jp nq thermal resistance junction to leads and exposed pad 0.95 k/w 13. pin v dd must not be used for any external supply 14. the ram content will not be altered above this voltage. 15. external resistance value seen from pin swi or hw, including 1 k series resistor. for the switch open, the maximum allowed leakage current is represented by a minimum resistance seen from the pin. 16. not applicable for ?product versions ncv70624dw010g, NCV70624DW010R2G?
amis ? 30624, ncv70624 http://onsemi.com 8 ac parameters the ac parameters are guaranteed for temperature and v bb in the operating range unless otherwise specified. table 6. ac parameters symbol pin(s) parameter test conditions min typ max unit powerup t pu power ? up time guaranteed by design 10 ms internal oscillator f osc frequency of internal oscillator v bb = 14 v 3.6 4.0 4.4 mhz i 2 c transceiver (standard mode) f scl sda sck scl clock frequency 100 khz t hd,start hold time (repeated) start condition. after this period the first clock pulse is generated. 4.0 s t low low period of the sck clock 4.7 s t high high period of the sck clock 4.0 s t su,start set ? up time for a repeated start condition 4.7 s t hd,data data hold time for i 2 c bus devices 0 (note 18) 3.45 (note 19) s t su,data data set ? up time 250 ns t r rise time of sda and sck signals 1.0 s t f fall time of sda and sck signals 0.3 s t su,stop set ? up time for stop condition 4.0 s t buf bus free time between stop and start condition 4.7 s i 2 c transceiver (fast mode) f scl sda sck scl clock frequency 360 khz t hd,start hold time (repeated) start condition. after this period the first clock pulse is generated. 0.6 s t low low period of the sck clock 1.3 s t high high period of the sck clock 0.6 s t su,start set ? up time for a repeated start condition 0.6 s t hd,data data hold time for i 2 c bus devices 0 (note 18) 0.9 (note 19) s t su,data data set ? up time 100 (note 20) ns t r rise time of sda and sck signals 20 + 0.1 c b 300 ns t f fall time of sda and sck signals 20 + 0.1 c b 300 ns t su,stop set ? up time for stop condition 0.6 s t buf bus free time between stop and start condition 1.3 s 17. the maximum number of connected i 2 c devices is dependent on the number of available addresses and the maximum bus capacitance to still guarantee the rise and fall times of the bus signals. 18. an i 2 c device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 19. the maximum t hd,dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 20. a fast ? mode i 2 c ? bus device can be used in a standard ? mode i 2 c bus system, but the requirement t su,data 250 ns must than be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch t he low period of the scl signal, it must output the next data bit to the sda line trmax + t su,data = 1000 + 250 = 1250 ns (according to the standard ? mode i 2 c ? bus specification) before the scl line is released.
amis ? 30624, ncv70624 http://onsemi.com 9 table 6. ac parameters symbol unit max typ min test conditions parameter pin(s) switch input and hardwire address input t sw swi hw scan pulse period (note 21) v bb = 14 v 1024 s t sw_on scan pulse duration (note 21) v bb = 14 v 128 s motordriver f pwm motxx pwm frequency (note 21) pwmfreq = 0 (note 22) 20.6 22.8 25.0 khz pwmfreq = 1 (note 22) 41.2 45.6 50.0 khz f jit_depth pwm jitter modulation depth pwmjen = 1 (note 22) 10 % t brise turn ? on transient time between 10% and 90% 140 ns t bfall turn ? off transient time 130 ns t stab run current stabilization time (note 21) 29 32 35 ms charge pump f cp cpn cpp charge pump frequency (note 21) v bb = 14 v 250 khz 21. derived from the internal oscillator 22. see setmotorparam and pwm regulator figure 5. i 2 c timing diagrams sda sck t f t hd,start t low t r t hd,data t su,data t high start repeated start t su,start t sp t su,stop t buf start stop v ihmin v ilmax
amis ? 30624, ncv70624 http://onsemi.com 10 typical application amis ? 30624, gnd 2 motxp tst2 100 nf 2,7 nf motxn motyp motyn 11 vdd vbb 12 vcp swi cpp cpn 9 8 sda sck 10 hw 18 m 16 15 13 20 tst1 3 vbb 19 1 6 54 71417 100 nf 220 nf 2,7 nf 1 k 1 k figure 6. typical application diagram for so device v bat c 8 c 1 connect to v bat or gnd c 7 100 f c 2 connect to v bat or gnd c 4 100 nf c 3 c 5 c 6 220 nf ncv70624 i 2 c bus notes: all resistors are ? 5%, 1/4 w c 1 , c 2 minimum value is 2.7 nf, maximum value is 10 nf depending on the application, the esr value and working voltage of c 7 must be carefully chosen c 3 and c 4 must be close to pins v bb and gnd c 5 and c 6 must be as close as possible to pins cpn, cpp, vcp, and v bb to reduce emc radiation c 9 must be a ceramic capacitor to assure low esr
amis ? 30624, ncv70624 http://onsemi.com 11 positioning parameters stepping modes one of four possible stepping modes can be programmed: ? half ? stepping ? 1/4 micro ? stepping ? 1/8 micro ? stepping ? 1/16 micro ? stepping maximum velocity for each stepping mode, the maximum velocity vmax can be programmed to 16 possible values given in the table below. the accuracy of vmax is derived from the internal oscillator. under special circumstances it is possible to change the vmax parameter while a motion is ongoing. all 16 entries for the vmax parameter are divided into four groups. when changing vmax during a motion the application must take care that the new vmax parameter stays within the same group. table 7. maximum velocity selection table vmax index vmax (full step/s) group stepping mode hex dec half ? stepping (half ? step/s) 1/4 th micro ? stepping (micro ? step/s) 1/8 th micro ? stepping (micro ? step/s) 1/16 th micro ? stepping (micro ? step/s) 0 0 99 a 197 395 790 1579 1 1 136 b 273 546 1091 2182 2 2 167 334 668 1335 2670 3 3 197 395 790 1579 3159 4 4 213 425 851 1701 3403 5 5 228 456 912 1823 3647 6 6 243 486 973 1945 3891 7 7 273 c 546 1091 2182 4364 8 8 303 607 1213 2426 4852 9 9 334 668 1335 2670 5341 a 10 364 729 1457 2914 5829 b 11 395 790 1579 3159 6317 c 12 456 912 1823 3647 7294 d 13 546 d 1091 2182 4364 8728 e 14 729 1457 2914 5829 11658 f 15 973 1945 3891 7782 15564
amis ? 30624, ncv70624 http://onsemi.com 12 minimum velocity once the maximum velocity is chosen, 16 possible values can be programmed for the minimum velocity vmin. the table below provides the obtainable values in full ? step/s. the accuracy of vmin is derived from the internal oscillator. table 8. obtainable values in full ? step/s for the minimum velocity vmin index vmax factor vmax (full ? step/s) a b c d hex dec 99 136 167 197 213 228 243 273 303 334 364 395 456 546 729 973 0 0 1 99 136 167 197 213 228 243 273 303 334 364 395 456 546 729 973 1 1 1/32 3 4 5 6 6 7 7 8 8 10 10 11 13 15 19 27 2 2 2/32 6 8 10 11 12 13 14 15 17 19 21 23 27 31 42 57 3 3 3/32 9 12 15 18 19 21 22 25 27 31 32 36 42 50 65 88 4 4 4/32 12 16 20 24 26 28 30 32 36 40 44 48 55 65 88 118 5 5 5/32 15 21 26 31 32 35 37 42 46 51 55 61 71 84 111 149 6 6 6/32 18 25 31 36 39 42 45 50 55 61 67 72 84 99 134 179 7 7 7/32 21 30 36 43 46 50 52 59 65 72 78 86 99 118 156 210 8 8 8/32 24 33 41 49 52 56 60 67 74 82 90 97 113 134 179 240 9 9 9/32 28 38 47 55 59 64 68 76 84 93 101 111 128 153 202 271 a 10 10/32 31 42 51 61 66 71 75 84 93 103 113 122 141 168 225 301 b 11 11/32 34 47 57 68 72 78 83 93 103 114 124 135 156 187 248 332 c 12 12/32 37 51 62 73 79 85 91 101 113 124 135 147 170 202 271 362 d 13 13/32 40 55 68 80 86 93 98 111 122 135 147 160 185 221 294 393 e 14 14/32 43 59 72 86 93 99 106 118 132 145 158 172 198 237 317 423 f 15 15/32 46 64 78 93 99 107 113 128 141 156 170 185 214 256 340 454 notes: the vmax factor is an approximation. in case of motion without acceleration ( accshape = 1 ) the length of the steps = 1/ vmin. in case of accelerated motion ( accshape = 0) the length of the first step is shorter than 1/ vmin depending of vmin, vmax and acc .
amis ? 30624, ncv70624 http://onsemi.com 13 acceleration and deceleration sixteen possible values can be programmed for acc (acceleration and deceleration between vmin and vmax). the table below provides the obtainable values in full ? step/s 2 . one observes restrictions for some combinations of acceleration index and maximum speed (gray cells). the accuracy of acc is derived from the internal oscillator. table 9. acceleration and deceleration selection table vmax (fs/s) 99 136 167 197 213 228 243 273 303 334 364 395 456 546 729 973 acc index acceleration (full ? step/s 2 ) hex dec 0 0 49 106 473 1 1 218 735 2 2 1004 3 3 3609 4 4 6228 5 5 8848 6 6 11409 7 7 13970 8 8 16531 9 9 14785 19092 a 10 21886 b 11 24447 c 12 27008 d 13 29570 e 14 29570 34925 f 15 40047 the formula to compute the number of equivalent full ? steps during acceleration phase is: nstep vmax 2 vmin 2 2 acc positioning the position programmed in command setposition is given as a number of (micro ? )steps. according to the chosen stepping mode, the position words must be aligned as described in the table below. when using command gotosecureposition , data is automatically aligned. table 10. position word alignment stepping mode position word: pos[15:0] shift 1/16 th s b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 lsb no shift 1/8 th s b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 lsb 0 1 ? bit left ? ? 2 1/4 th s b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 lsb 0 0 2 ? bit left ? ? 4 half ? stepping s b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 lsb 0 0 0 3 ? bit left ? ? 8 secureposition s b9 b8 b7 b6 b5 b4 b3 b2 b1 lsb 0 0 0 0 0 no shift notes: lsb: least significant bit s: sign bit
amis ? 30624, ncv70624 http://onsemi.com 14 position ranges a position is coded by using the binary two?s complement format. according to the positioning commands used and to the chosen stepping mode, the position range will be as shown in the following table. table 11. position range command stepping mode position range full range excursion number of bits setposition half ? stepping ? 4096 to +4095 8192 half ? steps 13 1/4 th micro ? stepping ? 8192 to +8191 16384 micro ? steps 14 1/8 th micro ? stepping ? 16384 to +16383 32768 micro ? steps 15 1/16 th micro ? stepping ? 32768 to +32767 65536 micro ? steps 16 when using the command setposition , although coded on 16 bits, the position word will have to be shifted to the left by a certain number of bits, according to the stepping mode. secure position a secure position can be programmed. it is coded in 11 ? bits, thus having a lower resolution than normal positions, as shown in the following table. see also command gotosecureposition . table 12. secure position stepping mode secure position resolution half ? stepping 4 half ? steps 1/4 th micro ? stepping 8 micro ? steps (1/4 th ) 1/8 th micro ? stepping 16 micro ? steps (1/8 th ) 1/16 th micro ? stepping 32 micro ? steps (1/16 th ) important notes: the secure position is disabled in case the programmed value is the reserved code ?10000000000? (0x400 or most negative position). the resolution of the secure position is limited to 9 bit at start ? up. the otp register is copied in ram as illustrated below. the ram bits secpos1 and secpos0 are set to 0. secpos10 secpos9 secpos8 secpos2 secpos1 secpos0 secpos10 secpos9 secpos8 secpos2 ram otp shaft a shaft bit, which can be programmed in otp or with command setmotorparam , defines whether a positive motion is a clockwise (cw) or counter ? clockwise rotation (ccw) (an outer or an inner motion for linear actuators): ? shaft = 0 ? motxp is used as positive pin of the x coil, while motxn is the negative one. ? shaft = 1 ? opposite situation exception: in runvelocity mode, the shaft bit has no function. in this mode the rotational direction is always cw or ccw, which is only determined by the motor wiring. structural description see also the block diagram in figure 1. stepper motordriver the motordriver receives the control signals from the control logic. the main features are: ? two h ? bridges, designed to drive a stepper motor with two separated coils. each coil (x and y) is driven by one h ? bridge, and the driver controls the currents flowing through the coils. the rotational position of the rotor, in unloaded condition, is defined by the ratio of current flowing in x and y. the torque of the stepper motor when unloaded is controlled by the magnitude of the currents in x and y. ? the control block for the h ? bridges, including the pwm control, the synchronous rectification and the internal current sensing circuitry. ? the charge pump to allow driving of the h ? bridges? high side transistors. ? two pre ? scale 4 ? bit dac?s to set the maximum magnitude of the current through x and y.
amis ? 30624, ncv70624 http://onsemi.com 15 ? two dac?s to set the correct current ratio through x and y. battery voltage monitoring is also performed by this block, which provides the required information to the control logic part. the same applies for detection and reporting of an electrical problem that could occur on the coils or the charge pump. control logic (position controller and main control) the control logic block stores the information provided by the i 2 c interface (in a ram or an otp memory) and digitally controls the positioning of the stepper motor in terms of speed and acceleration, by feeding the right signals to the motordriver state machine. it will take into account the successive positioning commands to properly initiate or stop the stepper motor in order to reach the set point in a minimum time. it also receives feedback from the motordriver part in order to manage possible problems and decide on internal actions and reporting to the i 2 c interface. motion detection motion detection is based on the back ? emf generated internally in the running motor. when the motor is blocked, e.g. when it hits the end position, the velocity, and as a result also the generated back ? emf, is disturbed. the amis ? 30624/ncv70624 senses the back ? emf, calculates a moving average and compares the value with two independent threshold levels. if the back ? emf disturbance is bigger than the set threshold, the running motor is stopped. miscellaneous the amis ? 30624/ncv70624 also contains the following: ? an internal oscillator, needed for the control logic handler as well as the control logic and the pwm control of the motordriver. ? an internal trimmed voltage source for precise referencing. ? a protection block featuring a thermal shutdown and a power ? on ? reset circuit. ? a 5 v regulator (from the battery supply) to supply the internal logic circuitry. functions description this chapter describes the following functional blocks in more detail: ? position controller ? main control and register, otp memory + rom ? motordriver the motion detection and i 2 c controller are discussed in separate chapters. position controller positioning and motion control a positioning command will produce a motion as illustrated in figure 7. a motion starts with an acceleration phase from minimum velocity (vmin) to maximum velocity (vmax) and ends with a symmetrical deceleration. this is defined by the control logic according to the position required by the application and the parameters programmed by the application during the configuration phase. the current in the coils is also programmable. velocity vmax vmin acceleration range deceleration range pstart pstop p=0 position zero speed hold current pmin pmax zero speed hold current figure 7. positioning and motion control
amis ? 30624, ncv70624 http://onsemi.com 16 table 13. position related parameters parameter reference pmax ? pmin see positioning zero speed hold current see ihold maximum current see irun acceleration and deceleration see acceleration and deceleration vmin see minimum velocity vmax see maximum velocity different positioning examples are shown in the table below. table 14. positioning examples short motion. velocity time new positioning command in same dir- ection, shorter or longer, while a motion is running at maximum velocity. velocity time new positioning command in same dir- ection while in deceleration phase (note 23) note: there is no wait time between the deceleration phase and the new accel- eration phase. velocity time new positioning command in reverse direction while motion is running at max- imum velocity. velocity time new positioning command in reverse direction while in deceleration phase. velocity time new velocity programming while motion is running. velocity time 23. reaching the end position is always guaranteed, however velocity rounding errors might occur after consecutive accelerations during a deceleration phase. the velocity rounding error will be removed at vmin (e.g. at end of acceleration or when accshape=1).
amis ? 30624, ncv70624 http://onsemi.com 17 dual positioning a setdualposition command allows the user to perform a positioning using two different velocities. the first motion is done with the specified vmin and vmax velocities in the setdualposition command, with the acceleration (deceleration) parameter already in ram, to a position pos1[15:0] also specified in setdualposition . then a second relative motion to a physical position pos1[15:0] + pos2[15:0] is done at the specified vmin velocity in the setdualposition command (no acceleration). once the second motion is achieved, the actpos register is reset to zero, whereas tagpos register is not changed. when the secure position is enabled, after the dual positioning, the secure positioning is executed. the figure below gives a detailed overview of the dual positioning function. after the dual positioning is executed an internal flag is set to indicate the amis ? 30624/ncv70624 is referenced. vmax tstab vmin tstab assume: first position = 300 second position = 5 secure position = 50 pos: xx actpos: 300 actpos: 0 resetpos 01 actpos: 0 4 resetpos during one vmin time the actpos is 0 secure (if enabled) positioning second first movement profile: motion status: position: 00 00 0 xx 5 steps when stall detection is enabled, this movement is stopped when a stall is detected. 0 0 1 0 0 50 a new motion will start only after tstab figure 8. dual positioning actpos: 50 movement remark: this operation cannot be interrupted or influenced by any further command unless the occurrence of the conditions driving to a motor shutdown or by a hardstop command. sending a setdualposition command while a motion is already ongoing is not recommended. 24. the priority encoder is describing the management of states and commands. 25. a dualposition sequence starts by setting tagpos buffer register to secpos value, provided secure position is enabled otherw ise tagpos is reset to zero. if a setposition(short) command is issued during a dualposition sequence, it will be kept in the position buf fer memory and executed afterwards. this applies also for the command gotosecureposition . 26. commands such as getfullstatus1 or getfullstatus2 will be executed while a dual positioning is running. 27. the pos1, pos2, vmax and vmin values programmed in a setdualposition command apply only for this sequence. all other motion parameters are used from the ram registers (programmed for instance by a former setmotorparam command). after the dualposition motion is completed, the former vmin and vmax become active again. 28. commands resetposition, setdualposition, and softstop will be ignored while a dualposition sequence is ongoing, and will not be executed afterwards. 29. recommendation: a setmotorparam command should not be sent during a setdualposition sequence: all the motion parameters defined in the command, except vmin and vmax, become active immediately. position periodicity depending on the stepping mode the position can range from ? 4096 to +4095 in half ? step to ? 32768 to +32767 in 1/16th micro ? stepping mode. one can project all these positions lying on a circle. when executing the command setposition , the position controller will set the movement direction in such a way that the traveled distance is minimal. the figure below illustrates that the moving direction going from actpos = +30000 to tagpos = ?30000 is clockwise. if a counter clockwise motion is required in this example, several consecutive setposition commands can be used. one could also use for lar ger movements the command runvelocity .
amis ? 30624, ncv70624 http://onsemi.com 18 0 actpos = +30000 tagpos = ? 30000 ? 10000 ? 20000 +10000 +20000 motion direction figure 9. motion direction is function of difference between actpos and tagpos hardwired address hw in the drawing below, a simplified schematic diagram is shown of the hw comparator circuit. the hw pin is sensed via 2 switches. the drivehs and drivels control lines are alternatively closing the top and bottom switch connecting hw pin with a current to resistor converter. closing s top (drivehs = 1) will sense a current to gnd. in that case the top i r converter output is low, via the closed passing switch s pass_t this signal is fed to the ?r? comparator which output hw_cmp is high. closing bottom switch s bot (drivels = 1) will sense a current to v bat . the corresponding i r converter output is low and via s pass_b fed to the comparator. the output hw_cmp will be high. 12 3 1 = r2gnd comp i/r logic high low float drivehs drivels hw_cmp hw state debouncer debouncer 64 ms 1 k figure 10. simplified schematic diagram of the hw comparator s bot s top i/r r th 32 s s pass_b ??r? ? comp s pass_t 2 = r2vbat 3 = open 3 cases can be distinguished (see also figure 10 above): ? hw is connected to ground: r2gnd or drawing 1 ? hw is connected to vbat: r2vbat or drawing 2 ? hw is floating: open or drawing 3
amis ? 30624, ncv70624 http://onsemi.com 19 table 15. state diagram of the hw comparator previous state drivels drivehs hw_cmp new state condition drawing float 1 0 0 float r2gnd or open 1 or 3 float 1 0 1 high r2vbat 2 float 0 1 0 float r2vbat or open 2 or 3 float 0 1 1 low r2gnd 1 low 1 0 0 low r2gnd or open 1 or 3 low 1 0 1 high r2vbat 2 low 0 1 0 float r2vbat or open 2 or 3 low 0 1 1 low r2gnd 1 high 1 0 0 float r2gnd or open 1 or 3 high 1 0 1 high r2vbat 2 high 0 1 0 high r2vbat or open 2 or 3 high 0 1 1 low r2gnd 1 the logic is controlling the correct sequence in closing the switches and in interpreting the 32 s debounced hw_cmp output accordingly. the output of this small state ? machine is corresponding to: ? high or address = 1 ? low or address = 0 ? floating as illustrated in the table above (table 15), the state is depending on the previous state, the condition of the 2 switch controls (drivels and drivehs) and the output of hw_cmp. figure 11 shows an example of a practical case where a connection to vbat is interrupted.
amis ? 30624, ncv70624 http://onsemi.com 20 t drivels t t drivehs hw_cmp state t r2 vbat open high r2 vbat r2 gnd t float figure 11. timing diagram showing the change in states for hw comparator float high r th condition ?r? ? comp tsw = 1024 s tsw_on = 128 s t low r2vbat a resistor is connected between vbat and hw. every 1024 s s bot is closed and a current is sensed. the output of the i ? r converter is low and the hw_cmp output is high. assuming the previous state was floating, the internal logic will interpret this as a change of state and the new state will be high (see also table 15). the next time s bot is closed the same conditions are observed. the previous state was high so based on table 15 the new state remains unchanged. this high state will be interpreted as hw address = 1. open in case the hw connection is lost (broken wire, bad contact in connector) the next time s bot is closed, this will be sensed. there will be no current, the output of the corresponding i ? r converter is high and the hw_cmp will be low. the previous state was high. based in table 15 one can see that the state changes to float. this will trigger a motion to secure position after a debounce time of 64 ms, which prevents false triggering in case of micro ? interruptions of the power supply. r2gnd if a resistor is connected between hw and the gnd, a current is sensed every 1024 s when s top is closed. the output of the top i ? r converter is low and as a result the hw_cmp output switches to high. again based on the stated diagram in t able 15 one can see that the state will change to low. this low state will be interpreted as hw address = 0. external switch swi as illustrated in figure 12 the swi comparator is almost identical to hw. the major difference is in the limited number of states. only open or closed is recognized leading to respectively esw = 0 and esw = 1.
amis ? 30624, ncv70624 http://onsemi.com 21 comp i/r logic closed open drivehs drivels swi_cmp swi 12 3 1 = r2gnd 1 k figure 12. simplified schematic diagram of the swi comparator 2 = r2vbat 3 = open s bot s top 32 s debouncer r th i/r state s pass_b s pass_t ??r? ? comp as illustrated in the drawing above, a change in state is always synchronized with drivehs or drivels. the same synchronization is valid for updating the internal position register. this means that after every current pulse (or closing of s top or s bot ) the state of the position switch together with the corresponding position is memorized. the fullstatus1 command reads back the register and the status of esw. in this way the master node may get synchronous information about the state of the switch together with the position of the motor. see table 16 below. table 16. getfullstatus1 i 2 c command getfullstatus1 response frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 1 1 address 1 1 1 otp3 otp2 otp1 otp0 hw 2 data 1 irun[3:0] ihold[3:0] 3 data 2 vmax[3:0] vmin[3:0] 4 data 3 accshape stepmode[1:0] shaft acc[3:0] 5 data 4 vddreset steploss eldef uv2 tsd tw tinfo[1:0] 6 data 5 motion[2:0] esw ovc1 ovc2 stall cpfail 7 data 6 1 1 1 1 1 1 1 1 8 data 7 absthr[3:0] delthr[3:0]
amis ? 30624, ncv70624 http://onsemi.com 22 drivehs t t t drivels swi_cmp esw t t 0111 actpos t figure 13. simplified timing diagram showing the change in states for swi comparator actpos actpos + 1 actpos + 2 actpos + 3 r th ?r? ? comp 512 s 120 s tsw = 1024 s tsw_on = 128 s main control and register, otp memory + rom power ? up phase power ? up phase of the amis ? 30624/ncv70624 will not exceed 10 ms. after this phase, the amis ? 30624/ncv70624 is in standby mode, ready to receive i 2 c messages and execute the associated commands. after power ? up, the registers and flags are in the reset state, while some of them are being loaded with the otp memory content (see table 19: ram registers). reset after power ? up, or after a reset occurrence (e.g. a micro ? cut on pin v bb has made v dd to go below vddreset level), the h ? bridges will be in high ? impedance mode, and the registers and flags will be in a predetermined position. this is documented in table 19: ram registers and table 20: flags table. soft ? stop a soft ? stop is an immediate interruption of a motion, but with a deceleration phase. at the end of this action, the register is loaded with the value contained in register , see table 19: ram registers). the circuit is then ready to execute a new positioning command, provided thermal and electrical conditions allow for it.
amis ? 30624, ncv70624 http://onsemi.com 23 thermal shutdown mode when thermal shutdown occurs, the circuit performs a command and goes to motor shutdown mode (see figure 14: state diagram temperature management). temperature management the amis ? 30624/ncv70624 monitors temperature by means of two thresholds and one shutdown level, as illustrated in the state diagram and illustration of figure 14: state diagram temperature management below. the only condition to reset flags and (respectively thermal warning and thermal shutdown) is to be at a temperature lower than ttw and to get the occurrence of a getfullstatus1 i 2 c frame. normal temp. ? < tinfo > = ?00? ? < tw > = ?0? ? < tsd > = ?0? t ? < ttw & getfullstatus1 t ? > ttw thermal warning ? < tinfo >=? 10 ? ? < tw >=? 1 ? ? < tsd > = ?0? t ? > ttsd thermal shutdown ? < tinfo >=? 11 ? ? < tw > = ?1? ? < tsd >=? 1 ? ? softstop if motion ongoing ? motor shutdown (motion disabled) post thermal warning ? < tinfo >=? 00 ? ? < tw > = ?1? ? < tsd > = ?0? t ? > tlow t ? > ttw t ? < ttsd t ? > ttsd post thermal shutdown 1 ? < tinfo >=? 10 ? ? < tw > = ?1? ? < tsd > = ?1? ? motor shutdown (motion disabled) post thermal shutdown 2 ? < tinfo >=? 00 ? ? < tw > = ?1? ? < tsd > = ?1? ? motor shutdown (motion disabled) low temp. ? < tinfo >=? 01 ? ? < tw > = ?0? ? < tsd > = ?0? t ? < ttw t ? > ttw t ? < tlow t ? < ttw figure 14. state diagram temperature management i 2 c frame:
amis ? 30624, ncv70624 http://onsemi.com 24 t warning level t shutdown level t t getfullstatus1 t > ttsd, motor stops and shutdown getfullstatus1 figure 15. illustration of thermal management situation t bit t bit t < t tw and t < t tw and autarkic functionality in under ? voltage condition battery voltage management the amis ? 30624/ncv70624 monitors the battery voltage by means of one threshold and one shutdown level. the only condition to reset flags and is to recover by a battery voltage higher than uv1 and to receive a getfullstatus1 command. autarkic function the device enters states (see figure 16), followed by when v bb is below the uv2 level or = 1. the motion is stopped immediately and target position (t agpos) is kept and not overwritten by actual position (actpos). the motor is in hiz state and the flags and are set to inform the master that the voltage has dropped below uv2 or the charge pump voltage has dropped below the level of the charge pump comparator and loss of steps is possible. ? if in this state v bb becomes > uv1 within 15 seconds, then amis ? 30624/ncv70624 returns to state. from there, it resumes the interrupted motion and accepts updates of the target position by means of the commands setposition and gotosecureposition , even if the flag, the flag and flags are not cleared. ? if however the v bb voltage remains below uv2 level or the charge pump voltage level is below the charge pump comparator for more than 15 seconds, then the device will enter state and the target position is overwritten by actual position. this state can be exited only if v bb is > uv1, the charge pump voltage is above the charge pump comparator voltage and an incoming command getfullstatus1 is received. important notes: 1. in the case of autarkic positioning, care needs to be taken because accumulated steploss can cause a significant deviation between physical and stored actual position. 2. the setdualposition command will only be executed after clearing the , cpfail and flags. 3. ram reset occurs when vdd < vddreset (digital power ? on ? reset level). 4. the autarkic function remains active as long as v dd > vddreset.
amis ? 30624, ncv70624 http://onsemi.com 25 otp register otp memory structure the table below shows how the parameters to be stored in the otp memory are located. table 17. otp memory structure address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 osc3 osc2 osc1 osc0 iref3 iref2 iref1 iref0 0x01 0 tsd2 tsd1 tsd0 bg3 bg2 bg1 bg0 0x02 absthr3 absthr2 absthr1 absthr0 pa3 pa2 pa1 pa0 0x03 irun3 irun2 irun1 irun0 ihold3 ihold2 ihold1 ihold0 0x04 vmax3 vmax2 vmax1 vmax0 vmin3 vmin2 vmin1 vmin0 0x05 secpos10 secpos9 secpos8 shaft acc3 acc2 acc1 acc0 0x06 secpos7 secpos6 secpos5 secpos4 secpos3 secpos2 0x07 delthr3 delthr2 delthr1 delthr0 stepmode1 stepmode0 lockbt lockbg parameters stored at address 0x00 and 0x01 and bit are already programmed in the otp memory at circuit delivery. they correspond to the calibration of the circuit and are just documented here as an indication. each otp bit is at ?0? when not zapped. zapping a bit will set it to ?1?. thus only bits having to be at ?1? must be zapped. zapping of a bit already at ?1? is disabled. each otp byte will be programmed separately (see command setotpparam ). once otp programming is completed, bit can be zapped to disable future zapping, otherwise any otp bit at ?0? could still be zapped by using a setotpparam command. table 18. otp overwrite protection lock bit protected bytes lockbt (factory zapped before delivery) 0x00 to 0x01 lockbg 0x00 to 0x07 the command used to load the application parameters via the i 2 c bus in the ram prior to an otp memory programming is setmotorparam . this allows for a functional verification before using a setotpparam command to program and zap separately one otp memory byte. a getotpparam command issued after each setotpparam command allows verifying the correct byte zapping. note: zapped bits will become active only after a power cycle. after programming the i 2 c bits the power cycle has to be performed first to guarantee further communication with the device. application parameters stored in otp memory except for the physical address these parameters, although programmed in a non ? volatile memory can still be overridden in ram by a i 2 c writing operation. pa[3:0] in combination with hired wired (hw) address, it forms the physical address ad[6:0] of the stepper ? motor. up to 32 stepper motors can theoretically be connected to the same i 2 c bus. absthr[3:0] absolute threshold used for the motion detection index absthr absthr level (v) (*) 0 0 0 0 0 disable 1 0 0 0 1 0.5 2 0 0 1 0 1.0 3 0 0 1 1 1.5 4 0 1 0 0 2.0 5 0 1 0 1 2.5 6 0 1 1 0 3.0 7 0 1 1 1 3.5 8 1 0 0 0 4.0 9 1 0 0 1 4.5 a 1 0 1 0 5.0 b 1 0 1 1 5.5 c 1 1 0 0 6.0 d 1 1 0 1 6.5 e 1 1 1 0 7.0 f 1 1 1 1 7.5 (*) not tested in production. values are approximations.
amis ? 30624, ncv70624 http://onsemi.com 26 delthr[3:0] relative threshold used for the motion detection index delthr delthr level (v) (*) 0 0 0 0 0 disable 1 0 0 0 1 0.25 2 0 0 1 0 0.50 3 0 0 1 1 0.75 4 0 1 0 0 1.00 5 0 1 0 1 1.25 6 0 1 1 0 1.50 7 0 1 1 1 1.75 8 1 0 0 0 2.00 9 1 0 0 1 2.25 a 1 0 1 0 2.50 b 1 0 1 1 2.75 c 1 1 0 0 3.00 d 1 1 0 1 3.25 e 1 1 1 0 3.50 f 1 1 1 1 3.75 (*) not tested in production. values are approximations. irun[3:0] current amplitude value to be fed to each coil of the stepper ? motor. the table below provides the 16 possible values for . index irun run current (ma) 0 0 0 0 0 59 1 0 0 0 1 71 2 0 0 1 0 84 3 0 0 1 1 100 4 0 1 0 0 119 5 0 1 0 1 141 6 0 1 1 0 168 7 0 1 1 1 200 8 1 0 0 0 238 9 1 0 0 1 283 a 1 0 1 0 336 b 1 0 1 1 400 c 1 1 0 0 476 d 1 1 0 1 566 e 1 1 1 0 673 f 1 1 1 1 800 ihold[3:0] hold current for each coil of the stepper ? motor. the table below provides the 16 possible values for . index ihold hold current (ma) 0 0 0 0 0 59 1 0 0 0 1 71 2 0 0 1 0 84 3 0 0 1 1 100 4 0 1 0 0 119 5 0 1 0 1 141 6 0 1 1 0 168 7 0 1 1 1 200 8 1 0 0 0 238 9 1 0 0 1 283 a 1 0 1 0 336 b 1 0 1 1 400 c 1 1 0 0 476 d 1 1 0 1 566 e 1 1 1 0 673 f 1 1 1 1 0 note: when the motor is stopped, the current is reduced from to . in the case of 0 ma hold current (1111 in the hold current table), the following sequence is applied: 1. the current is first reduced to 59 ma (corresponding to 0000 value in the table). 2. the pwm regulator is switched off; the bottom transistors of the bridges are grounded. stepmode setting of step modes. stepmode step mode 0 0 1/2 stepping 0 1 1/4 stepping 1 0 1/8 stepping 1 1 1/16 stepping shaft this bit distinguishes between a clock ? wise or counter ? clock ? wise rotation. the shaft bit is not working in runvelocity mode. secpos[10:2] secure position of the stepper ? motor. this is the position to which the motor is driven in case of a hw pin connection is lost. if = ?100 0000 00xx?, secure positioning is disabled; the stepper ? motor will be kept in the position occupied at the moment these events occur.
amis ? 30624, ncv70624 http://onsemi.com 27 note: the secure position is coded on 11 bits only, providing actually the most significant bits of the position, the non coded least significant bits being set to ?0?. the secure position in otp has only 9 bits. the two least significant bits are loaded as ?0? to ram when copied from otp. vmax[3:0] maximum velocity index vmax vmax(full step/s) group 0 0 0 0 0 99 a 1 0 0 0 1 136 b 2 0 0 1 0 167 3 0 0 1 1 197 4 0 1 0 0 213 5 0 1 0 1 228 6 0 1 1 0 243 7 0 1 1 1 273 c 8 1 0 0 0 303 9 1 0 0 1 334 a 1 0 1 0 364 b 1 0 1 1 395 c 1 1 0 0 456 d 1 1 0 1 546 d e 1 1 1 0 729 f 1 1 1 1 973 vmin[3:0] minimum velocity. index vmin vmax factor 0 0 0 0 0 1 1 0 0 0 1 1/32 2 0 0 1 0 2/32 3 0 0 1 1 3/32 4 0 1 0 0 4/32 5 0 1 0 1 5/32 6 0 1 1 0 6/32 7 0 1 1 1 7/32 8 1 0 0 0 8/32 9 1 0 0 1 9/32 a 1 0 1 0 10/32 b 1 0 1 1 11/32 c 1 1 0 0 12/32 d 1 1 0 1 13/32 e 1 1 1 0 14/32 f 1 1 1 1 15/32 acc[3:0] acceleration and deceleration between vmax and vmin. index acc acceleration (full ? step/s 2 ) 0 0 0 0 0 49 (*) 1 0 0 0 1 218 (*) 2 0 0 1 0 1004 . 3 0 0 1 1 3609 . 4 0 1 0 0 6228 . 5 0 1 0 1 8848 . 6 0 1 1 0 11409 . 7 0 1 1 1 13970 . 8 1 0 0 0 16531 . 9 1 0 0 1 19092 (*) a 1 0 1 0 21886 (*) b 1 0 1 1 24447 (*) c 1 1 0 0 27008 (*) d 1 1 0 1 29570 (*) e 1 1 1 0 34925 (*) f 1 1 1 1 40047 (*) (*) restriction on speed
amis ? 30624, ncv70624 http://onsemi.com 28 table 19. ram registers register mnemonic length (bit) related commands comment reset state actual position actpos 16 getfullstatus2 gotosecurepos resetposition 16 ? bit signed last programmed position pos/tagpos 16/11 getfullstatus2 gotosecurepos resetposition setposition 16 ? bit signed or 11 ? bit signed for half stepping (see positioning ) acceleration shape accshape 1 getfullstatus1 setmotorparam resettodefault ?0? ? normal acceleration from vmin to vmax ?1? ? motion at vmin without acceleration ?0? coil peak current irun 4 getfullstatus1 setmotorparam resettodefault operating current see look ? up table irun from otp memory coil hold current ihold 4 getfullstatus1 setmotorparam resettodefault standstill current see look ? up table ihold minimum velocity vmin 4 getfullstatus1 setmotorparam resettodefault see section minimum velocity see look ? up table vmin maximum velocity vmax 4 getfullstatus1 setmotorparam resettodefault see section maximum velocity see look ? up table vmax shaft shaft 1 getfullstatus1 setmotorparam resettodefault direction of movement acceleration/ deceleration acc 4 getfullstatus1 setmotorparam resettodefault see section acceleration see look ? up table acc secure position secpos 11 getfullstatus2 setmotorparam resettodefault target position when hw connection fails; 11 msb?s of 16 ? bit position (lsb?s fixed to ?0?) stepping mode stepmode 2 getfullstatus1 setstallparam resettodefault see section stepping modes see look ? up table stepmode stall detection absolute threshold absthr 4 getfullstatus1 setstallparam resettodefault stall detection delta threshold delthr 4 getfullstatus1 setstallparam resettodefault stall detection delay fs2stallen 3 getfullstatus2 setstallparam delays the stall detection after acceleration ?000? stall detection sampling minsamples 3 getfullstatus2 setstallparam duration of the zero current step in number of pwm cycles. ?000? pwm jitter pwmjen 1 getfullstatus2 setstallparam ?1? means jitter is added ?0? 100% duty cycle stall enable dc100sten 1 getfullstatus2 setstallparam ?1? means stall detection is enabled in case pwm regulator runs at = 100% ?0? pwm frequency pwmfreq 1 setmotorparam ?0? means ~ 22 khz, ?1? means ~ 44 khz ?0? 30. a resettodefault command will act as a reset of the ram content, except for actpos and tagpos , which are registers that are not modified. therefore, the application should not send a resettodefault during a motion, to avoid any unwanted change of parameter.
amis ? 30624, ncv70624 http://onsemi.com 29 table 20. flags table flag mnemonic length (bit) related commands comment reset state charge pump failure cpfail 1 getfullstatus1 ?0? = charge pump ok ?1? = charge pump failure resets only after getfullstatus1 ?0? electrical defect eldef 1 getfullstatus1 or or ? open ? load on coil x ? or ? open ? load on coil x y or resets only after getfullstatus1 ?0? external switch status esw 1 getfullstatus1 ?0? = open ?1? = close ?0? electrical flag hs 1 internal use or or or ?0? motion status motion 3 getfullstatus1 ?x00? = stop ?001? = inner (ccw) motion acceleration ?010? = inner (ccw) motion deceleration ?011? = inner (ccw) motion max. speed ?101? = outer (cw) motion acceleration ?110? = outer (cw) motion deceleration ?111? = outer (cw) motion max. speed ?000? over current in coil x ovc1 1 getfullstatus1 ?1? = over current; reset only after getfull- status1 ?0? over current in coil y ovc2 1 getfullstatus1 ?1? = over current; reset only after getfull- status1 ?0? secure position enabled secen 1 internal use ?0? if = ?100 0000 0000? ?1? otherwise n.a. step loss steploss 1 getfullstatus1 ?1? = step loss due to under voltage, over current, open circuit or stall; resets only after getfull- status1 ?1? delta high stall delstallhi 1 getfullstatus2 ?1? = vbemf > ubemf + deltathr ?0? delta low stall delstalllo 1 getfullstatus2 ?1? = vbemf < ubemf ? deltathr ?0? absolute stall absstall 1 getfullstatus2 ?1? = vbemf < absthr ?0? stall stall 1 getfullstatus1 ?0? motor stop stop 1 internal use ?0? temperature info tinfo 2 getfullstatus1 ?00? = normal temperature range ?01? = low temperature warning ?10? = high temperature warning ?11? = motor shutdown ?00? thermal shutdown tsd 1 getfullstatus1 ?1? = shutdown (t j > t tsd ) resets only after getfullstatus 1 and if = ?00? ?0? thermal warning tw 1 getfullstatus1 ?1? = over temperature (t j > t tw ) resets only after getfullstatus 1 and if = ?00? ?0? battery stop voltage uv2 1 getfullstatus1 ?0? = v bb > uv2 ?1? = v bb ? uv2 resets only after getfullstatus1 ?0? digital supply reset vddreset 1 getactualpos getstatus getfullstatus1 set at ?1? after power ? up of the circuit. if this was due to a supply micro ? cut, it warns that the ram contents may have been lost; can be reset to ?0? with a get(full)status1 command ?1?
amis ? 30624, ncv70624 http://onsemi.com 30 priority encoder the table below describes the simplified state management performed by the main control block. table 21. priority encoder state standby stopped gotopos dualposition softstop hardstop shutdown hardunder shutunder command motor stopped, ihold in coils motor motion ongoing no influence on ram and tag- pos motor decelerating motor forced to stop motor stopped, h ? bridges in hi ? z getotpparam otp refresh; i 2 c slave response otp refresh; i 2 c slave response otp refresh; i 2 c slave response otp refresh; i 2 c slave response otp refresh; i 2 c slave response otp refresh; i 2 c slave response getfullstatus1 [attempt to clear all flags] (note 31) i 2 c slave response i 2 c slave response i 2 c slave response i 2 c slave response i 2 c slave response i 2 c slave response; if ( or = ?0? then ? stopped getfullstatus2 i 2 c slave response i 2 c slave response i 2 c slave response i 2 c slave response i 2 c slave response i 2 c slave response resettodefault [ actpos and tagpos are not altered ] otp refresh; otp to ram; accshape reset otp refresh; otp to ram; accshape reset otp refresh; otp to ram; accshape reset (note 33) otp refresh; otp to ram; accshape reset otp refresh; otp to ram; accshape reset otp refresh; otp to ram; accshape reset setmotorparam [master takes care about proper update] ram update ram update ram update ram update ram update ram update ram update ram update ram update resetposition and reset and reset and reset setposition updated; ? gotopos updated updated setpositionshort updated; ? gotopos updated updated gotosecposition if = ?1? then = ; ? gotopos if = ?1? then = if = ?1? then = dualposition ? dualposition softstop ? softstop hardstop ? hardstop ? hardstop ? hardstop v bb < uv2 and t > 15 seconds ? hardunder ? hardunder ? hardstop ? hardunder v bb < uv2 and t < 15 seconds ? stopped = ?1? ? = ?1? ? shutdown ? hardstop; = ?1? ? hardstop; = ?1? ? hardstop; = ?1? ? shutdown thermal shutdown [ = ?1?] ? shutdown ? softstop ? softstop ? shutdown motion finished n.a. ? stopped ? stopped ? stopped; = ? stopped; = n.a. with the following color code: command ignored transition to another state master is responsible for proper update (see note 36) note: see table notes on the following page.
amis ? 30624, ncv70624 http://onsemi.com 31 31. = or or or 32. after power ? on ? reset, the state is entered. 33. a dualposition sequence runs with a separate set of ram registers. the parameters that are not specified in a dualposition c ommand are loaded with the values stored in ram at the moment the dualposition sequence starts. is forced to ?1? during second motion. at ?0? will be taken into account after the dualposition sequence. a getfullstatus1 command will return the default parameters for < vmax> and stored in ram. 34. shutdown state can be left only when and flags are reset. 35. flags can be reset only after the master could read them via a getfullstatus1 command, and provided the physical conditions allow for it (normal temperature, correct battery voltage and no electrical or charge pump defect). 36. a setmotorparam command sent while a motion is ongoing (state ) should not attempt to modify and values. this can be done during a dualposition sequence since this motion uses its own parameters, the new parameters will be taken into acc ount at the next setposition command. 37. = ?1? when register is loaded with a value different from the most negative value (i.e. different from 0x400 = ?100 0000 0000?). 38. flag allows distinguishing whether state was entered after hardstop/softstop or not. is set to ?1? when leaving state or and is reset during first clock edge occurring in state . 39. while in state , if ? there is a transition to state . this transition has the lowest priority, meaning that , , etceteras are first evaluated for possible transitions. 40. if is active, then setposition and gotosecureposition commands are not ignored. can only be cleared by a getfullstatus1 command. hardstop stopped gotopos shutdown thermal shutdown hardstop hardstop hardstop dual positioning motion finished gotosecpos setposition motion finished motion finished thermal shutdown softstop hardstop thermal shutdown referencing soft ? stop priorities 1 2 3 4 motion finished por hardunder shutunder vbb < uv2 or cpfail vbb < uv2 or cpfail vbb > uv1 and not cpfail t > 15 sec figure 16. simplified state diagram getfullstatus1
amis ? 30624, ncv70624 http://onsemi.com 32 motordriver current waveforms in the coils figure 17 below illustrates the current fed to the motor coils by the motordriver in half ? step mode. t coil x coil y ix iy figure 17. current waveforms in motor coils x and y in halfstep mode whereas figure 18 below shows the current fed to the coils in 1/16 th micro stepping (1 electrical period). t coil x coil y ix iy figure 18. current waveforms in motor coils x and y in 1/16 th micro ? step mode pwm regulation in order to force a given current (determined by or and the current position of the rotor) through the motor coil while ensuring high energy transfer efficiency, a regulation based on pwm principle is used. the regulation loop performs a comparison of the sensed output current to an internal reference, and features a digital regulation generating the pwm signal that drives the output switches. the zoom over one micro ? step in the figure 18 above shows how the pwm circuit performs this regulation. to reduce the current ripple, a higher pwm frequency is selectable. the ram register pwmfreq is used for this. table 22. pwm frequency selection pwmfreq applied pwm frequency 0 22,8 khz 1 45,6 khz pwm jitter to lower the power spectrum for the fundamental and higher harmonics of the pwm frequency, jitter can be added to the pwm clock. the ram register is used for this. table 23. pwm jitter selection pwmjen status 0 single pwm frequency 1 added jitter to pwm frequency
amis ? 30624, ncv70624 http://onsemi.com 33 motor starting phase at motion start, the currents in the coils are directly switched from to with a new sine/cosine ratio corresponding to the first half (or micro ? ) step of the motion. motor stopping phase at the end of the deceleration phase, the currents are maintained in the coils at their actual dc level (hence keeping the sine/cosine ratio between coils) during the stabilization time t stab (see ac t able ). the currents are then set to the hold values, respectively ihold x sin( tagpos ) and ihold x cos( tagpos ), as illustrated below. a new positioning order can then be executed. t ix iy t stab figure 19. motor stopping phase charge pump monitoring if the charge pump voltage is not sufficient for driving the high side transistors (due to failure), an internal hardstop command is issued. this is acknowledged to the master by raising flag (available with command getfullstatus1 ). in case this failure occurs while a motion is ongoing, the flag is also raised. electrical defect on coils, detection and confirmation the principle relies on the detection of a voltage drop on at least one transistor of the h ? bridge. then the decision is taken to open the transistors of the defective bridge. this allows the detection the following short circuits: ? external coil short circuit ? short between one terminal of the coil and vbat or gnd one cannot detect an internal short in the motor. open circuits are detected by 100% pwm duty cycle value during one electrical period with duration, determined by vmin. table 24. electrical defect detection pins fault mode yi or xi short ? circuit to gnd yi or xi short ? circuit to vbat yi or xi open y1 and y2 short circuited x1 and x2 short circuited xi and yi short circuited motor shutdown mode a motor shutdown occurs when: ? the chip temperature rises above the thermal shutdown threshold ttsd (see thermal shutdown mode ). ? the battery voltage goes below uv2 for longer than 15 seconds (see battery voltage management ). ? the charge pump voltage goes below the charge pump comparator level for more than 15 seconds. ? flag = ?1?, meaning an electrical problem is detected on one or both coils, e.g. a short circuit. a motor shutdown leads to the following: ? h ? bridges in high impedance mode. ? the register is loaded with the , except in autarkic states. the conditions to get out of a motor shutdown mode are: ? reception of a getfullstatus1 command and ? the four above causes are no longer detected this leads to h ? bridges going in ihold mode. hence, the circuit is ready to execute any positioning command.
amis ? 30624, ncv70624 http://onsemi.com 34 this can be illustrated in the following sequence given as an application example. the master can check whether there is a problem or not and decide which application strategy to adopt. table 25. example of possible sequence used to detect and determine cause of motor shutdown tj ? ts d o r v bb ? uv2 (>15s) or < eldef > = ?1? or < cpfail > = ?1? (>15s) ? setposition frame ? getfullstatus1 frame ? getfullstatus1 frame ? ... ? the circuit is driven in motor shutdown mode ? the application is not aware of this ? the position set ? point is updated by the i 2 c master ? motor shutdown mode ? no motion ? the application is still unaware ? the application is aware of a problem ? possible confirmation of the problem ? reset < tw > or < tsd > or < uv2 > or < steploss > or < eldef > or < cpfail > by the application ? possible new detection of over temperature or low voltage or electrical problem ? circuit sets < tw > or < tsd > or < uv2 > or < steploss > or < eldef > or < cpfail > again at ?1? important: while in shutdown mode, since there is no hold current in the coils, the mechanical load can cause a step loss, which indeed cannot be flagged by the amis ? 30624/ncv70624. note: the priority encoder is describing the management of states and commands. warning: the application should limit the number of consecutive getfullstatus1 commands to try to get the amis ? 30624/ncv70624 out of shutdown mode when this proves to be unsuccessful, e.g. there is a permanent defect. the reliability of the circuit could be altered since getfullstatus1 attempts to disable the protection of the h ? bridges. motion detection motion detection is based on the back emf generated internally in the running motor. when the motor is blocked, e.g. when it hits the end ? stop, the velocity and as a result also the generated back emf, is disturbed. the amis ? 30624/ncv70624 senses the back emf, calculates a moving average and compares the value with two independent threshold levels: absolute threshold (absthr[3:0] ) and delta threshold ( ). instructions for correct use of these two levels in combination with three additional parameters ( , and ) are available in a dedicated application note ?robust motion control with amis ? 3062x stepper motor drivers?. if the motor is accelerated by a pulling or propelling force and the resulting back emf increases above the delta threshold (+ thr), then is set. when the motor is slowing down and the resulting back emf decreases below the delta threshold ( ? thr), then is set. when the motor is blocked and the velocity is zero after the acceleration phase, the back emf is low or zero. when this value is below the absolute threshold, is set. the flag is the or function of or or . absstall t velocity t motor speed vbemf v absth t back emf vbemf deltastallhi t t deltastalllo t figure 20. triggering of the stall flags in function of measured backemf and the set threshold levels v bemf v bemf v min v max + thr ? thr
amis ? 30624, ncv70624 http://onsemi.com 35 table 26. truth table condition vbemf < average ? delthr 1 0 0 1 vbemf > average + delthr 0 1 0 1 vbemf < absthr 0 0 1 1 by design, the motion will only be detected when the motor is running at the maximum velocity, not during acceleration or deceleration. if the motor is positioning when stall is detected, an (internal) hardstop of the motor is generated and the and flags are set. these flags can only be reset by sending a getfullstatus1 command. if stall appears during dualposition then the first phase is cancelled (via internal hardstop) and after timeout tstab (see ac table) the second phase at vmin starts. when the flag is set the position controller will generate an internal hardstop. as a consequence also the flag will be set. the position in the internal counter will be copied to the register. all flags can be read out with the getfullstatus1 command. important remark (limited to motion detection flags / parameters): using getfullstatus1 will read and clear the following flags: , , , and . new positioning is possible and the register will be further updated. motion detection is disabled when the ram registers and are zero. both levels can be programmed using the i 2 c command setstallparam in the registers and . also the otp register and can be set using the i 2 c command setotpparam . these values are copied in the ram registers during power on reset. table 27. absolute and delta threshold settings absthr index absthr level (v) (*) delthr index delthr level (v) (*) 0 disable 0 disable 1 0.5 1 0.25 2 1.0 2 0.50 3 1.5 3 0.75 4 2.0 4 1.00 5 2.5 5 1.25 6 3.0 6 1.50 7 3.5 7 1.75 8 4.0 8 2.00 9 4.5 9 2.25 a 5.0 a 2.50 b 5.5 b 2.75 c 6.0 c 3.00 d 6.5 d 3.25 e 7.0 e 3.50 f 7.5 f 3.75 (*) not tested in production. values are approximations. minsamples is a programmable delay timer. after the zero crossing is detected, the delay counter is started. after the delay time ? out (t delay ) the back ? emf sample is taken. for more information please refer to the application note ?robust motion control with amis ? 3062x stepper motor drivers?. table 28. back emf sample delay time index minsamples[2:0] t delay ( s) 0 000 87 1 001 130 2 010 174 3 011 217 4 100 261 5 101 304 6 110 348 7 111 391
amis ? 30624, ncv70624 http://onsemi.com 36 fs2stallen if or <> 0 (i.e. motion detection is enabled), then stall detection will be activated after the acceleration ramp + an additional number of full ? steps, according to the following table: table 29. activation delay of motion detection index fs2stallen[2:0] delay (full steps) 0 000 0 1 001 1 2 010 2 3 011 3 4 100 4 5 101 5 6 110 6 7 111 7 dc100sten when a motor with large bemf is operated at high speed and low supply voltage, then the pwm duty cycle can be as high as 100%. this indicates that the supply is too low to generate the required torque and might also result in erroneously triggering the stall detection. the bit enables stall detection when duty cycle is 100%. for more information please refer to the application note ?robust motion control with amis ? 3062x stepper motor drivers?. motion qualification mode (*) this mode is useful to debug motion parameters and to verify the stability of stepper motor systems. the motion qualification mode is entered by means of the i 2 c command testbemf . the swi pin will be converted into an analogue output on which the back emf integrator output can be measured. once activated, it can only be stopped after a por. during the back emf observation, reading of the swi state is internally forbidden. (*) note: not applicable for product versions ncv70624dw010g, NCV70624DW010R2G. more information is available in the application note ?robust motion control with amis ? 3062x stepper motor drivers?.
amis ? 30624, ncv70624 http://onsemi.com 37 i 2 c bus description general description amis ? 30624/ncv70624 uses a simple bi ? directional 2 ? wire bus for efficient inter ? ic control. this bus is called the inter ic or i 2 c ? bus. features include: ? only two bus lines are required; a serial data line (sda) and a serial clock line (sck). ? each device connected to the bus is software addressable by a unique address and simple master/slave relationships exists at all times; master can operate as master ? transmitter or as master receiver. ? serial, 8 ? bit oriented, bi ? directional data transfers can be made up to 400 kb/s. ? on ? chip filtering rejects spikes on the bus data line to preserve data integrity. ? no need to design bus interfaces because i 2 c ? bus interface is already integrated on ? chip. ? ic?s can be added to or removed from a system without affecting any other circuits on the bus. concept the i 2 c ? bus consists of two wires, serial data (sda) and serial clock (sck), carrying information between the devices connected on the bus. each device connected to the bus is recognized by a unique address and operates as either a transmitter or receiver, depending on the function of the device. amis ? 30624/ncv70624 can both receive and transmit data. in addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. amis ? 30624/ncv70624 is a slave device. see table 31. table 30. definition of i 2 c?bus terminology term description transmitter the device which sends data on the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the devices addressed by a master synchronization procedure to synchronizer the clock signals of two or more devices micro ? controller motordriver_1 amis ? 30624, motordriver_2 amis ? 30624, motordriver_3 amis ? 30624, motordriver_4 amis ? 30624, sda scl ncv70624 ncv70624 figure 21. example of an i 2 c ? bus configuration using one microcontroller and four slaves ncv70624 ncv70624 figure 21 highlights the master ? slave and receiver ? transmitter relationships to be found on the i 2 c ? bus. it should be noted that these relationships are not permanent but only depend on the direction of data transfer at that time. the transfer of data would proceed as follows: 1. suppose the microcontroller wants to send information to motordriver_1: ? microcontroller (master) addresses motordriver_1 (slave) ? microcontroller (master ? transmitter) sends data to motordriver_1 (slave ? receiver) ? microcontroller terminates the transfer 2. if the microcontroller wants to receive information from motordriver_2: ? microcontroller (master) addresses motordriver_2 (slave) ? microcontroller (master ? receiver) receives data from motordriver_2 (slave ? transmitter) ? microcontroller terminates the transfer even in this case the master generates the timing and terminates the transfer. generation of the signals on the i 2 c ? bus is always the responsibility of the master device. it generates its own clock signal when transferring data on the bus. bus clock signals from a master can only be altered when they are stretched by a slow slave device holding ? down the clock line.
amis ? 30624, ncv70624 http://onsemi.com 38 general characteristics serial clock line serial data line r p +5 v clock in clock out data in data out amis ? 30624, sda sck scl sda clock in clock out data in data out master r p 21 figure 22. connection of a device to the i 2 c ? bus ncv70624 both sda and sck are bi ? directional lines connected to a positive supply voltage via a pull ? up resistor (see figure 22). when the bus is free both lines are high. the output stages of the devices connected to the bus must have an open drain to perform the wired ? and function. data on the i 2 c ? bus can be transferred up to 400 kb/s in fast mode. the number of interfaces connected to the bus is dependent on the maximum bus capacitance limit (see c b in table 6) and the available number of addresses. bit transfer the levels for logic ?0? (low) and ?1? (high) are not fixed in the i 2 c standard but dependent on the used v dd level. using amis ? 30624/ncv70624, the levels are specified in table 5. one clock pulse is generated for each data bit transferred. data validity the data on the sda line must be stable during the high period of the clock. the high or low state of the data line can only change when the clock signal on the scl line is low (see figure 23). sck data line stable ? > data valid sda change of data allowed figure 23. bit transfer on the i 2 c ? bus start and stop conditions within the procedure of the i 2 c ? bus, unique situations arise, which are defined as start (s) and stop (p) conditions (see figure 24). a high to low transition on the sda line while sck is high is one such unique case. this situation indicates a start condition. low to high transition on the sda line while sck is high defines a stop condition. start and stop conditions are always generated by the master. the bus is considered to be busy after the start condition. the bus is considered to be free again a certain time after the stop condition. the bus free situation is specified as t buf in table 6. the bus stays busy if a repeated start (sr) is generated instead of a st op condition. in this respect, the start (s) and repeated start (sr) conditions are functionally identical (see figure 25). the symbol s will be used to represent start and repeated start, unless otherwise noted. start stop sck start condition stop condition sda figure 24. start and stop conditions
amis ? 30624, ncv70624 http://onsemi.com 39 transferring data byte format every byte put on the sda line must be 8 ? bits long. the number of bytes that can be transmitted per transfer to amis ? 30624/ncv70624 is restricted to eight. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first (see figure 25). if a slave can?t receive or transmit another complete byte of data, it can hold the clock line sck low to force the master into a wait state. data transfer then continues when the slave is ready for another byte of data and releases clock line sck. sda start stop sck 12 78 9 12 3 ? 8 9 acknowledgement signal from slave clock line held low by slave aknowledge related clock puse from master start condition ack msb stop condition figure 25. data transfer on the i 2 c ? bus acknowledge data transfer with acknowledge is obligatory. the acknowledge ? related clock pulse is generated by the master. the transmitter releases the sda line (high) during the acknowledge clock pulse. the receiver must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse (see figure 26). of course, set ? up and hold times must also taken into account (see table 6). when amis ? 30624/ncv60624 doesn?t acknowledge the slave address, the data line will be left high. the master can than generate either a stop condition to abort the transfer, or a repeated start condition to start a new transfer. if amis ? 30624/ncv60624 as slave ? receiver does acknowledge the slave address but later in the transfer cannot receive any more data bytes, this is indicated by generating a not ? acknowledge on the first byte to follow. the master generates than a stop or a repeated start condition. if a master ? receiver is involved in the transfer, it must signal the end of data to the slave ? transmitter by not generating an acknowledge on the last byte that was clocked out of the slave. amis ? 30624/ncv70624 as slave ? transmitter shall release the data line to allow the master to generate stop or repeated start condition. sda by master transmitter start sck from master 12 89 master releases the data line slave pulls data line low if acknowledged aknowledge related clock puse from master start condition acknowledged msb sda by slave receiver not acknowledged figure 26. acknowledge on the i 2 c ? bus
amis ? 30624, ncv70624 http://onsemi.com 40 clock generation the master generates the clock on the sck line to transfer messages on the i 2 c ? bus. data is only valid during the high period of the clock. data formats with 7 ? bit addresses data transfers follow the format shown in figure 27. after the start condition (s), a slave address is sent. this address is 7 ? bit long followed by an eighth bit which is a data direction bit (r/w) ? a ?zero? indicates a transmission (write), a ?one? indicates a request for data (read). a data transfer is always terminated by a stop condition (p) generated by the master. start stop sck start condition stop condition 1 ? 7 8 9 1 ? 7 89 1 ? 7 8 9 ack r/w address data ack data ack sda figure 27. a complete data transfer however, if a master still wishes to communicate on the bus, it can generate a repeated start (sr) and address another slave without first generating a stop condition. various combinations of read/write formats are then possible within such a transfer. data transfer formats writing data to amis ? 30624/ncv70624 when writing to amis ? 30624/ncv70624, the master ? transmitter transmits to slave ? receiver and the transfer direction is not changed. a complete transmission consists of: ? start condition ? the slave address (7 ? bit) ? read/write bit (?0? = write) ? acknowledge bit ? any further data bytes are followed by an acknowledge bit. the acknowledge bit is used to signal a correct reception of the data to the transmitter. in this case the amis ? 30624/ncv70624 pulls the sda line to ?0?. the amis ? 30624/ncv70624 reads the incoming data at sda on every rising edge of the sck signal ? stop condition to finish the transmission n bytes + acknowledge master to amis ? 30624 amis ? 30624 to master s = start condition p = stop condition a = acknowledge (sda = low) a = no acknowledge (sda = high) s slave address r/w a data a data a p ?0? = write figure 28. master writing data to amis ? 30624/ncv70624 some commands for the amis ? 30624/ncv70624 are supporting eight bytes of data, other commands are transmitting two bytes of data. see table 31. reading data to amis ? 30624/ncv70624 when reading data from amis ? 30624/ncv70624 two transmissions are needed: 1. the first transmission consists of two bytes of data: ? the first byte contains the slave address and the write bit. ? the second byte contains the address of an internal register in the amis ? 30624/ncv70624. this internal register address is stored in the circuit ram.
amis ? 30624, ncv70624 http://onsemi.com 41 s slave address r/w a internal address ?0? = write a p figure 29. master reading data from amis ? 30624/ncv70624: first transmission is addressing 2. the second transmission consists of the slave address and the read bit. then the master can read the data bits on the sda line on every rising edge of signal sck. after each byte of data the master has to acknowledge correct data reception by pulling sda low. the last byte is not acknowledged by the master and therefore the slave knows the end of transmission. n bytes + acknowledge master to amis ? 30624 amis ? 30624 to master s = start condition p = stop condition a = acknowledge (sda = low) a = no acknowledge (sda = high) s slave address r/w a data a data a p ?0? = write figure 30. master reading data from amis ? 30624/ncv70624: second transmission is reading data notes: 1. each byte is followed by an acknowledgment bit as indicated by the a or a in the sequence. 2. i 2 c ? bus compatible devices must reset their bus logic on receipt of a start condition such that they all anticipate the sending of a slave address, even if these start conditions are not positioned according to the proper format. 3. a start condition immediately followed by a stop condition (void message) is an illegal format. 7 ? bit addressing the addressing procedure for the i 2 c ? bus is such that the first byte after the start condition usually determines which slave will be selected by the master. the exception is the general call address which can call all devices. when this address is used all devices should respond with an acknowledge. the second byte of the general call address then defines the action to be taken. definition of bits in the first byte the first seven bits of the first byte make up the slave address. the eighth bit is the least significant bit (lsb). it determines the direction of the message. if the lsb is a ?zero? it means that the master will write information to a selected slave. a ?one? in this position means that the master will read information from the slave. when an address is sent, each device in a system compares the first seven bits after the start condition with its address. if they match, the device considers itself addressed by the master as a slave ? receiver or slave ? transmitter, depending on the r/w bit. r/w msb lsb slave address figure 31. first byte after start procedure amis ? 30624/ncv70624 is provided with a physical address in order to discriminate this circuit from other circuits on the i 2 c bus. this address is coded on seven bits (two bits being internally hardwired to ?1?), yielding the theoretical possibility of 32 different circuits on the same bus. it is a combination of four otp memory bits (otp memory structure open ) and of the externally hardwired address bits (pin hw). hw must either be connected to ground or to v bat . when hw is not connected and is left floating, correct functionality of the positioner is not guaranteed. the motor will be driven to the programmed secure position (see hardwired address ? open). r/w msb lsb otp memory 1 1 pa3 pa2 pa1 pa0 hw hardwired address bit figure 32. first byte after start procedure general call address the amis ? 30624/ncv70624 supports also a ?general call? address ?000 0000?, which can address all devices. when this address is used all devices should respond with an acknowledge. the second byte of the general call address then defines the action to be taken.
amis ? 30624, ncv70624 http://onsemi.com 42 i 2 c application commands introduction communications between the amis ? 30624/ncv70624 and a 2 ? wire serial bus interface master takes place via a large set of commands. reading commands are used to: ? get actual status information, e.g. error flags ? get actual position of the stepper motor ? verify the right programming and configuration of the amis ? 30624/ncv70624. writing commands are used to: ? program the otp memory ? configure the positioner with motion parameters (max/min speed, acceleration, stepping mode, etc.) ? provide target positions to the stepper motor the i 2 c ? bus master will have to use commands to manage the different application tasks the amis ? 30624/ncv70624 can feature. the commands summary is given in table 31. commands table table 31. i 2 c commands with corresponding rom pointer command mnemonic function command byte binary hexadecimal getfullstatus1 returns complete status of the chip ?1000 0001? 0x81 getfullstatus2 returns actual, target and secure position ?1111 1100? 0xfc getotpparam returns otp parameter ?1000 0010? 0x82 gotosecureposition drives motor to secure position ?1000 0100? 0x84 hardstop immediate full stop ?1000 0101? 0x85 resetposition sets actual position to zero ?1000 0110? 0x86 resettodefault overwrites the chip ram with otp contents ?1000 0111? 0x87 setdualposition drives the motor to two different positions with different speed ?1000 1000? 0x88 setmotorparam sets motor parameter ?1000 1001? 0x89 setotp zaps the otp memory ?1001 0000? 0x90 setposition programs a target and secure position ?1000 1011? 0x8b setstallparam sets stall parameters ?1001 0110? 0x96 softstop motor stopping with deceleration phase ?1000 1111? 0x8f runvelocity drives motor continuously ?1001 0111? 0x97 testbemf outputs bemf voltage on pin swi ?1001 1111? 0x9f these commands are described hereafter, with their corresponding i 2 c frames. refer to data transfer formats for more details. a color coding is used to distinguish between master and slave parts within the frames. an example is shown below. figure 33. color code used in the definition of i 2 c frames light gray: master data white: slave response
amis ? 30624, ncv70624 http://onsemi.com 43 application commands getfullstatus1 this command is provided to the circuit by the master to get a complete status of the circuit and of the stepper motor. refer to tables 19 and 20 to see the meaning of the parameters sent back to the i 2 c master. note : a getfullstatus1 command will attempt to reset flags < tw >, < tsd >, < uv2 >, < eldef >, < steploss >, < cpfail >, < ovc1 >, < ovc2 >, and . getfullstatus1 corresponds to the following i 2 c command frame: table 32. getfullstatus1 command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 0 0 0 1 table 33. getfullstatus1 response frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 1 1 address 1 1 1 otp3 otp2 otp1 otp0 hw 2 data 1 irun[3:0] ihold[3:0] 3 data 2 vmax[3:0] vmin[3:0] 4 data 3 accshape stepmode[1:0] shaft acc[3:0] 5 data 4 vddreset steploss eldef uv2 tsd tw tinfo[1:0] 6 data 5 motion[2:0] esw ovc1 ovc2 stall cpfail 7 data 6 1 1 1 1 1 1 1 1 8 data 7 absthr[3:0] delthr[3:0] where : otp(n) otp address bits pa[3:0] hw hardwired address bit irun[3:0] operating current in the motor coil ihold[3:0] standstill current in the motor coil vmax[3:0] maximum velocity vmin[3:0] minimum velocity accshape enables motion without acceleration stepmode[1:0] step mode definition shaft direction of movement acc[3:0] acceleration form minimum to maximum velocity vddreset reset of digital supply steploss step loss occurred eldef electrical defect uv2 battery under voltage detected tsd thermal shutdown tw thermal warning tinfo[1:0] temperature info motion[2:0] motion status esw external switch status ovc1 over current in x ? coil detected ovc2 over current in y ? coil detected stall stall detected cpfail charge pump failure absthr[3:0] stall detection absolute threshold delthr[3:0] stall detection delta threshold
amis ? 30624, ncv70624 http://onsemi.com 44 getfullstatus2 this command is provided to the circuit by the master to get the actual, target and secure position of the stepper motor. both the actual and target position are returned in signed two?s complement 16 ? bit format. secure position is coded in 10 ? bit format. according to the programmed stepping mode the lsbs of actpos[15:0] and tagpos[15:0] may have no meaning and should be assumed to be ?0?. this command also gives additional information concerning stall detection. refer to tables 19 and 20 to see the meaning of the parameters sent back to the i 2 c master. getfullstatus2 corresponds to the following i2c command frame: table 34. getfullstatus2 command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 1 1 1 1 1 0 0 table 35. getfullstatus2 response frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 1 1 address 1 1 1 otp3 otp2 otp1 otp0 hw 2 data 1 actpos[15:8] 3 data 2 actpos[7:0] 4 data 3 tagpos[15:8] 5 data 4 tagpos[7:0] 6 data 5 secpos[7:0] 7 data 6 fs2stallen[2:0] 1 dc100 secpos[10:8] 8 data 7 absstall delstalllo delstallhi minsamples[2:0] dc100sten pwmjen where : otp(n) otp address bits pa[3:0] hw hardwired address bit actpos[15:0] actual position tagpos[15:0] target position secpos[10:0] secure position fs2stallen[2:0] number of full steps after stall detection is enabled dc100 flag indicating pwm is at 100 percent duty cycle absstall stall detected because the absolute threshold is not reached delstalllo stall detected because the delta threshold is under crossed delstallhi: stall detected because the delta threshold is crossed minsamples[2:0] back ? emf sampling delay time dc100sten enables the switch off of stall detection when dc100 = 1 pwmjen pwm jitter enable
amis ? 30624, ncv70624 http://onsemi.com 45 getotpparam this command is provided to the circuit by the i 2 c master to read the content of the otp memory. more information can be found in otp memory structure corresponds to the following i 2 c command frame: . getotpparam table 36. getotpparam command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 0 0 1 0 table 37. getotpparam response frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 1 1 otp byte 0 otp byte @0x00 2 otp byte 1 otp byte @0x01 3 otp byte 2 otp byte @0x02 4 otp byte 3 otp byte @0x03 5 otp byte 4 otp byte @0x04 6 otp byte 5 otp byte @0x05 7 otp byte 6 otp byte @0x06 8 otp byte 7 otp byte @0x07 gotosecureposition this command is provided by the i 2 c master to one or all the stepper motors to move to the secure position secpos[10:0] . see the priority encoder corresponds to the following i 2 c command frame: description for more details. the priority encoder table also acknowledges the cases wh ere a gotosecureposition command will be ignored. gotosecureposition table 38. gotosecureposition command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 0 1 0 0
amis ? 30624, ncv70624 http://onsemi.com 46 hardstop this command will be internally triggered when an electrical problem is detected in one or both coils, leading to shutdown mode. if this occurs while the motor is moving, the < steploss > flag is raised to allow warning of the i 2 c master at the next getstatus1 command that steps may have been lost. once the motor is stopped, actpos register is copied into tagpos register to ensure keeping the stop position. the i 2 c master for some safety reasons can also issue a hardstop command. hardstop corresponds to the following i 2 c command frame: table 39. hardstop command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 0 1 0 1 resetposition this command is provided to the circuit by the i 2 c master to reset actpos and tagpos registers to zero. this can be helpful to prepare for instance a relative positioning. resetposition corresponds to the following i 2 c command frame: table 40. resetposition command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 0 1 1 0 resettodefault this command is provided to the circuit by the i 2 c master in order to reset the whole slave node into the initial state. resettodefault will, for instance, overwrite the ram with the reset state of the registers parameters (see t able 19). this is another way for the i 2 c master to initialize a slave node in case of emergency, or simply to refresh the ram content. note : actpos and tagpos are not modified by a resettodefault command. important : care should be taken not to send a resettodefault command while a motion is ongoing, since this could modify the motion parameters in a way forbidden by the position controller. resettodefault corresponds to the following i 2 c command frame: table 41. resettodefault command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 0 1 1 1 runvelocity this command is provided to the circuit by the i 2 c master in order to put the motor in continuous motion state. runvelocity corresponds to the following i 2 c command frame: table 42. runvelocity command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 1 0 1 1 1
amis ? 30624, ncv70624 http://onsemi.com 47 setdualposition this command is provided to the circuit by the i 2 c master in order to perform a positioning of the motor using two different velocities. see section dual positioning . note : this sequence cannot be interrupted by another positioning command. important : if for some reason actpos equals pos1[15:0] at the moment the setdualposition command is issued, the circuit will enter in deadlock state. therefore, the application should check the actual position by a getfullstatus2 corresponds to the following i 2 c command frame command prior to starting a dual positioning. another solution may consist of programming a value out of the stepper motor range for pos1[15:0] . for the same reason pos2[15:0] should not be equal to pos1[15:0]. setdualposition table 43. setdualposition command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 1 0 0 0 2 data 1 1 1 1 1 1 1 1 1 3 data 2 1 1 1 1 1 1 1 1 4 data 3 vmax[3:0] vmin[3:0] 5 data 4 pos1[15:8] 6 data 5 pos1[7:0] 7 data 6 pos2[15:8] 8 data 7 pos2[7:0] where : vmax[3:0] max. velocity for first motion vmin[3:0] min. velocity for first motion and velocity for the second motion pos1[15:0] first position to be reached during the first motion pos2[15:0] relative position of the second motion setstallparam this command sets the motion detection parameters and the related stepper motor parameters, such as the minimum and maximum velocity, the run ? and hold current, acceleration and step ? mode. see motion detection corresponds to the following i 2 c command frame for the meaning of these parameters. setstallparam table 44. setstallparam command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 1 0 1 1 0 2 data 1 1 1 1 1 1 1 1 1 3 data 2 1 1 1 1 1 1 1 1 4 data 3 irun[3:0] ihold[3:0] 5 data 4 vmax[3:0] vmin[3:0] 6 data 5 minsamples[2:0] shaft acc[3:0] 7 data 6 absthr[3:0] delthr[3:0] 8 data 7 fs2stallen[2:0] accsha pe stepmode[1:0] dc100s ten pwmje n
amis ? 30624, ncv70624 http://onsemi.com 48 setmotorparam this command is provided to the circuit by the i 2 c master to set the values for the stepper motor parameters (listed below) in ram. refer to t able 19 to see the meaning of the parameters sent by the i 2 c master. important : if a setmotorparam occurs while a motion is ongoing, it will modify at once the motion parameters (see position controller corresponds to the following i 2 c command frame:). therefore the application should not change parameters other than vmax while a motion is running, otherwise correct positioning cannot be guaranteed. setmotorparam table 45. setmotorparam command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 1 0 0 1 2 data 1 1 1 1 1 1 1 1 1 3 data 2 1 1 1 1 1 1 1 1 4 data 3 irun[3:0] ihold[3:0] 5 data 4 vmax[3:0] vmin[3:0] 6 data 5 secpos[10:8] shaft acc[3:0] 7 data 6 secpos[7:0] 8 data 7 1 pwmfre q 1 accsha pe stepmode[1:0] 1 pwmje n setotpparam this command is provided to the circuit by the i 2 c master to program and zap the otp data d[7:0] in otp address otpa[2:0] . important : this command must be sent under a specific v bb voltage value. see parameter v bb otp in t able 5. this is a mandatory condition to ensure reliable zapping. setotpparam corresponds to the following i 2 c command frame: table 46. setotpparam command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 1 0 0 0 0 2 data 1 1 1 1 1 1 1 1 1 3 data 2 1 1 1 1 1 1 1 1 4 data 3 1 1 1 1 1 otpa[2:0] 5 data 4 d[7:0] where : otpa[2:0]: otp address d[7:0]: corresponding otp data
amis ? 30624, ncv70624 http://onsemi.com 49 setposition this command is provided to the circuit by the i 2 c master to drive the motor to a given absolute position. see positioning (see priority encoder) for more details. the priority encoder table acknowledges the cases where a setposition command will be ignored. setposition corresponds to the following i 2 c command frame: table 47. setposition command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 1 0 1 1 2 data 1 1 1 1 1 1 1 1 1 3 data 2 1 1 1 1 1 1 1 1 4 data 3 pos[15:8] 5 data 4 pos[7:0] where : pos [15:0] signed 16 ? bit position set ? point for motor. softstop this command will be internally triggered when the chip temperature rises above the thermal shutdown threshold (see table 5 and the temperature management section). it provokes an immediate deceleration to vmin (see minimum velocity corresponds to the following i 2 c command frame:) followed by a stop, regardless of the position reached. once the motor is stopped, tagpos register is overwritten with value in actpos register to ensure keeping the stop position. the i 2 c master for some safety reasons can also issue a softstop command. softstop table 48. softstop command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 0 1 1 1 1 testbemf this command is provided to the circuit by the i 2 c master in order to output the bemf integrator output to the swi output of the chip. once activated, it can be stopped only after por. during the bemf observation, reading of the swi state is internally forbidden. testbemf corresponds to the following i 2 c command frame: table 49. testbemf command frame byte content structure bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 address 1 1 otp3 otp2 otp1 otp0 hw 0 1 command 1 0 0 1 1 1 1 1
amis ? 30624, ncv70624 http://onsemi.com 50 package dimensions soic 20 w case 751aq ? 01 issue o
amis ? 30624, ncv70624 http://onsemi.com 51 package dimensions nqfp ? 32, 7x7 case 560aa ? 01 issue o
amis ? 30624, ncv70624 http://onsemi.com 52 nqfp ? 32, 7x7 case 560aa ? 01 issue o on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 amis ? 30624/d the products described herein (amis ? 30624, ncv70624) may be covered by the following u.s. patents: 7,271,993 and 7,288,956. there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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